The use of configurable integrated circuits (“ICs”) has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array (“FPGA”). An FPGA is a field programmable IC that often has logic circuits, interconnect circuits, and input/output (“I/O”) circuits. The logic circuits (also called logic blocks) are typically arranged as an internal array of repeated arrangements of circuits. These logic circuits are typically connected together through numerous interconnect circuits (also called interconnects). The logic and interconnect circuits are often surrounded by the I/O circuits.
FIG. 1 illustrates an example of a configurable logic circuit 100. This logic circuit can be configured to perform a number of different functions. As shown in FIG. 1, the logic circuit 100 receives a set of input data 105 and a set of configuration data 110. The configuration data set is stored in a set of SRAM cells 115. From the set of functions that the logic circuit 100 can perform, the configuration data set specifies a particular function that this circuit has to perform on the input data set. Once the logic circuit performs its function on the input data set, it provides the output of this function on a set of output lines 120. The logic circuit 100 is said to be configurable, as the configuration data set “configures” the logic circuit to perform a particular function, and this configuration data set can be modified by writing new data in the SRAM cells. Multiplexers and look-up tables are two examples of configurable logic circuits.
FIG. 2 illustrates an example of a configurable interconnect circuit 200. This interconnect circuit 200 connects a set of input data 205 to a set of output data 210. This circuit receives configuration data 215 that are stored in a set of SRAM cells 220. The configuration data specify how the interconnect circuit should connect the input data set to the output data set. The interconnect circuit 200 is said to be configurable, as the configuration data set “configures” the interconnect circuit to use a particular connection scheme that connects the input data set to the output data set in a desired manner. Moreover, this configuration data set can be modified by writing new data in the SRAM cells. Multiplexers are one example of interconnect circuits.
FIG. 3A illustrates a portion of a prior art configurable IC 300. As shown in this figure, the IC 300 includes an array of configurable logic circuits 305 and configurable interconnect circuits 310. The IC 300 has two types of interconnect circuits 310a and 310b. Interconnect circuits 310a connect interconnect circuits 310b and logic circuits 305, while interconnect circuits 310b connect interconnect circuits 310a to other interconnect circuits 310a. 
In some cases, the IC 300 includes numerous logic circuits 305 and interconnect circuits 310 (e.g., hundreds, thousands, hundreds of thousands, etc. of such circuits). As shown in FIG. 3A, each logic circuit 305 includes additional logic and interconnect circuits. Specifically, FIG. 3A illustrates a logic circuit 305a that includes two sections 315a that together are called a slice. Each section includes a look-up table (“LUT”) 320, a user register 325, a multiplexer 330, and possibly other circuitry (e.g., carry logic) not illustrated in FIG. 3A.
The multiplexer 330 is responsible for selecting between the output of the LUT 320 or the user register 325. For instance, when the logic circuit 305a has to perform a computation through the LUT 320, the multiplexer 330 selects the output of the LUT 320. Alternatively, this multiplexer selects the output of the user register 325 when the logic circuit 305a or a slice of this circuit needs to store data for a future computation of the logic circuit 305a or another logic circuit.
FIG. 3B illustrates an alternative way of constructing half a slice in a logic circuit 305a of FIG. 3A. Like the half-slice 315a in FIG. 3A, the half-slice 315b in FIG. 3B includes a LUT 320, a user register 325, a multiplexer 330, and possibly other circuitry (e.g., carry logic) not illustrated in FIG. 3B. However, in the half-slice 315b, the user register 325 can also be configured as a latch. In addition, the half-slice 315b also includes a multiplexer 350. In half-slice 315b, the multiplexer 350 receives the output of the LUT 320 instead of the register/latch 325, which receives this output in half-slice 315a. The multiplexer 350 also receives a signal from outside of the half-slice 315b. Based on its select signal, the multiplexer 350 then supplies one of the two signals that it receives to the register/latch 325. In this manner, the register/latch 325 can be used to store (1) the output signal of the LUT 320 or (2) a signal from outside the half-slice 315b. 
The use of user registers to store such data is at times undesirable, as it typically requires data to be passed at a clock's rising edge or a clock's fall edge. In other words, registers often do not provide flexible control over the data passing between the various circuits of the configurable IC. In addition, the placement of a register or a latch in the logic circuit increases the signal delay through the logic circuit, as it requires the use of at least one multiplexer 330 to select between the output of a register/latch 325 and the output of a LUT 320. The placement of a register or a latch in the logic circuit further hinders the design of an IC as the logic circuit becomes restricted to performing either storage operations or logic operations, but not both.
Accordingly, there is a need for a configurable IC that has a more flexible approach for storing data and passing data that utilizes and is compatible with the IC's existing routing pathways and circuit array structures. More generally, there is a need for more flexible storage and routing mechanisms in configurable ICs.